The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.18 micron and under, e.g., 0.15 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.18 micron and under challenges the limitations of conventional interconnection technology, such as the electrical isolation properties of inter-layer dielectric (ILD) materials.
A problem encountered in highly miniaturized semiconductor devices employing multiple levels and reduced interwiring spacings in both the horizontal and vertical dimensions is related to the resistance-capacitance (RC) time constant of the system. Although semiconductor devices are presently being scaled in the horizontal dimension, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density that could exceed reliability limits. Horizontal scaling, however, requires conductive lines having a high aspect ratio, i.e., ratios of conductor height to conductor width greater than one, e.g., three or four, along with reduced interwiring spacings. As a consequence, capacitive coupling between conductive lines becomes a significant limitation on circuit speed. If intrametal capacitance is high, electrical inefficiencies and inaccuracies increase. It has been recognized that a reduction in capacitance within a multi-level system will reduce the RC time constant between the conductive lines.
The drive towards increased miniaturization and the resultant increase in the RC time constant have served as an impetus for the development of newer, low dielectric constant materials as substitutes for conventional higher dielectric constant ILD materials. Such low dielectric constant materials must be able to serve a number of different purposes requiring diverse characteristics and attributes. In particular, the ILD material must be able to fill deep, narrow gaps between closely spaced conductors; and undergo planarization of uneven surface topography so that a relatively flat level of conductors can be reliably deposited thereon as well as effectively insulate adjacent conductive lines. The diverse needs imposed upon ILD materials has been partly satisfied by employing highly porous low dielectric constant materials between conductive lines and features.
Conventionally, a wiring pattern comprising a dense array of conductive lines is formed by depositing a metal layer on an insulator and etching the metal layer to form a conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spaces therebetween. A low dielectric constant material, typically comprising a porous dielectric material, is then applied to the wiring pattern and the surface planarized by chemical-mechanical polishing techniques. A through-hole is formed in the ILD layer to expose a selected portion of an underlying metal feature, the exposed portion of the metal feature at the bottom of the through-hole serving as a contact pad. Upon filling the through-hole with conductive material, such as a metal plug, to form a conductive via, the bottom surface of the conductive via is in electrical contact with the underlying metal feature.
Additional layers are then deposited to complete a particular device. However, it has been extremely difficult to planarize the higher performing, porous low dielectric constant materials due to their increased tendency to decompose under physical and mechanical pressure.
Conventional planarization is effected by plasma etching, or by a simplified faster and relatively inexpensive method known as chemical-mechanical planarization or polishing (CMP). CMP is a conventional technique as disclosed in, see for example, Lee et al., U.S. Pat. No. 5,766,058; Salugsugan, U.S. Pat. No. 5,486,265 and Salugsugan, U.S. Pat. No. 5,245,794 the disclosures of which are herein incorporated in their entirety by reference.
In employing conventional CMP, wafers to be polished are mounted on a rotatable carrier assembly which is placed on the CMP apparatus. A polishing pad is adapted to engage the wafers carried by the carrier assembly and a chemical slurry containing a cleaning agent is dripped onto the pad continuously during the polishing operation. The chemical slurry is selected to provide an abrasive medium and chemical etching activity. Polishing involves the mechanical action of applying pressure to the wafers while rotating the wafers against the polishing pad which are wetted with the chemical slurry. However, in employing conventional CMP techniques, it is difficult to planarize a low dielectric constant material, particularly a porous material. The higher performing, lower dielectric constant materials tend to have less structural integrity and consequently are prone to being crushed or otherwise decomposed during the mechanical polishing process.
Accordingly, a need exists for polishing dielectric layers, particularly porous dielectric materials, as employed in the manufacture of ultra large scale integration semiconductor devices having multiple levels.